Because of trends in process technology, scaling, and the frequency of operations for VLSI devices, power consumption has become a dominant issue in integrated circuit design. Managing power consumption is thus a high priority in the design objectives of these devices.
It is broadly recognized in the implementation of power management systems for VLSI devices that the most efficient means of power management is to simultaneously change 1) the voltage delivered to an integrated circuit, and 2) the frequency of that integrated circuit's operation. Because voltage is a primary determinant of switching speed for transistors of an integrated circuit, a designer will typically specify the maximum frequency at which a part can operate for a given voltage. Thus, for an example micro-processor, a power supply may generate a fixed voltage of 2 volts to a device and the device may be specified as operating at 2 GigaHertz (GHz). However, the design of the device has to be such that the voltage seen at the integrated circuit is never below the level that enables the full 2 GHz operation. If the voltage on the integrated circuit falls below that level, there could be a timing failure and some of the components would be unable to switch fast enough to make the 2 GHz cycle times.
But power supplies vary and electrical parasitics between the power supply and the actual transistors of an integrated circuit effect power transmission. Thus the voltage actually delivered to an integrated circuit is not a completely fixed value, but rather ripples and varies with time. On average these ripples may have a total magnitude of approximately + or −10% of the total voltage. If the intent is to deliver 2 volts to the integrated circuit, the actual delivered voltage may vary between 1.8 volts and 2.2 volts. Since the voltage in large part determines the switching speed of components, designers have to make sure that (in the current example) the device in use can still operate at 2 GHz even if the delivered voltage is 1.8 volts. This is a technique known as guardbanding. Without this guardbanding, the integrated circuit could fail when the voltage drops.
For power consumption, two relationships become important when the voltage varies. One is the relationship of the device speed to voltage; a relationship that is approximately linear. If the voltage applied to a transistor is lowered by 10%, the switching speed of that transistor is reduced by approximately 10%. A first order approximation can be shown as:F∝ν  (1)
The second relationship is between power and frequency. Power (the total wattage dissipated by an integrated circuit) is equal to the switching capacitance of a device (a relatively fixed value for a given design, labeled C), multiplied by the voltage across the device squared (labeled V), and multiplied by the frequency at which the device is switching (plus a leakage term which may be disregarded here). This relationship is thus:P=C×V2×F  (2)
Using the previous example, if the capacitance on a component is switching once per cycle, then the capacitance is switching at a rate of 2 GHz, (or once every 500 picoseconds). Equation 2 show that a reduction in voltage would result in a square law reduction in power. For example, when voltage (V) drops 10%, becomes 0.9×V, the square law reduction causes the power (P) to be 0.9×0.9×P, or 0.81×P (a 19% reduction).
As equation 1 indicates, frequency is directly proportional to voltage. Thus when combined with equation 2, a reduction in frequency will lead to an additional voltage factor in power reduction. This results in power being reduced by approximately V3. Using the previous example, a 10% drop in V would result in a 0.9×0.9×0.9×P (0.72×P or 28%) reduction in power for a 10% reduction in voltage. This relationship is well known, and has been exploited for power management particularly in mobile devices such as laptops.
Many power-management solutions use software to minimize the excess computing power of microprocessors and other like devices. Based upon an expected load, the software determines how fast the processor must operate; for example, the software may note that a densely coded application may require more speed than a simple one. Once the software determines the speed required by the demand, it can reduce the speed to only that which is required. The result is a reduction in the power consumption for the device over time.
However, these methods lead to inefficiencies in voltage management. For example, these methods require that a software program predict the computing demands an integrated circuit may see and then change the voltage and frequency accordingly. This results in lag times associated with prediction inaccuracies. Further, the intention of these systems is to minimize the total energy consumed over time for the processor. Portable units, such as laptops, can then maximize the battery life with these algorithms. For a server type processor, minimizing total energy usage over a period of time is not the goal. Maximum computing power is the goal. Within a given power envelope, a server system should maximize the performance that is available on demand for a customer. Ideally, the full performance capability should be available at any time to a customer. Even in server systems, however, there are significant motivations for keeping the power down. For example, as a chip bums power it generates heat that is difficult to draw away from a small silicon die. Further, it is more expensive to run a large number of processors at higher power, and it is difficult to provide that power in tight spaces. Thus, for a server, a system that only tries to minimize power when the compute needs are high does not suffice; the compute needs are always high. Likewise, a system that simply provides maximum computing power is insufficient for most systems. Thus, there exists a need for a method that actively optimizes the power consumed while maintaining the system's ability to deliver the highest performance without having to rely on software predictions that are often inaccurate.
An additional shortcoming of currently available solutions is the time lag between the recognition that an opportunity to reduce power (or the recognition of the need to increase power due to high compute needs) and the operation that effects that change. After recognition, a command to vary voltage must be sent out to a voltage regulator which generates the voltage used by the processor. It then takes a number of microseconds (10s to 100s of microseconds, typically) for the voltage regulator to perform that task. It is not until that voltage transition is completed that the frequency can actually be raised on the processor itself, because a processor running at a frequency higher than the voltage supports can result in a timing failure. Thus, there is a time lag waiting for the voltage to slew before the frequency can be raised. Similarly, in order to lower the voltage (to reduce the power consumption) the frequency must be lowered first to avoid a timing failure caused by a voltage too low for a given frequency. A system that understood exactly how fast the integrated circuit could operate for a given voltage, combined with a system that could operate the chip at a frequency matched to that voltage, would result in a significant efficiency gains. Instead of anticipating a voltage reduction and lowering frequency in advance, such a system could lower voltage and frequency together. Such a system could also avoid the guardbanding necessary when a designer is required to anticipate the varying operating conditions of a device. If, using the above example, the voltage varies by + or −10%, a designer must ensure that the device will work at its quoted frequency if only 90% of the expected voltage is provided. Thus, there exists a need for a system that could set the frequency to an observed voltage and constantly vary the frequency to match the voltage actually delivered.
In order to further improve efficiencies, many power-management systems shut off parts of an integrated circuit that are not in use. For example, the floating point computation unit in a microprocessor is a high performance unit that is needed for technical code. For many applications (word processing, transaction processing, and other general integer applications) the floating point computation is unnecessary. A typical power-savings method might shut the clock down to the floating point unit so that it is not using power. But as units on an integrated circuit are powered up and down, the processor can experience large, sudden changes in power consumption. This poses a challenge to the power delivery system, because there is always some resistance and some inductance between the components and the power supply. Further, a sudden spike in power to dormant areas can result in a voltage drop to already powered sections that can cause operational and timing problems. Thus, there exists a need for a system that can adapt very rapidly to changes in voltage induced by sudden changes in power consumption.